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PI6C20400
1:4 Clock Driver for Intel PCI Express Chipsets
Features
* Four Pairs of Differential Clocks * Low skew < 50ps * Low jitter < 50ps * Output Enable for all outputs * Outputs tristate control via SMBus * Power Management Control * Programmable PLL Bandwidth * PLL or Fanout operation * 3.3V Operation * Packaging: - 28-Pin SSOP (H) & 28-Pin TSSOP (L) - Pb-Free and Green Option (HE and LE)
Description
Pericom Semiconductors PI6C20400 is a high-speed, low-noise differential clock buffer designed to be companion to PI6C410B. The device distributes the differential SRC clock from PI6C410B to four differential pairs of clock outputs either with or without PLL. The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When input of either SRC_STOP# or PWRDWN# is low, the output clocks are Tristated. When PWRDWN# is low, the SDA and SCLK inputs must be Tristated.
Block Diagram
OE_INV OE_0 & OE_3 SRC_STOP# PWRDWN# SCLK SDA PLL/BYPASS# SRC SRC# Output Control
Pin Configuration
VDD SRC SCR# VSS VDD OUT0 OUT0# OE_0 OUT1 OUT1# VDD PLL/BYPASS# SCLK SDA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
OUT0 OUT0# OUT0 OUT1# OUT2 OUT2# OUT3 OUT3#
SMBus Controller
PLL_BW#
PLL
DIV
VDD_A VSS_A IREF OE_INV VDD OUT3 OUT3# OE_3 OUT2 OUT2# VDD PLL_BW# SRC_STOP# PWRDWN#
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PI6C20400 1:4 Clock Driver for Intel PCI Express Chipsets Pin Descriptions
Pin Name SRC & SRC# OE_0 & OE_3 Type Input Input 2, 3 8, 21 Pin No Description 0.7V Differential SRC input from PI6C410 clock synthesizer 3.3V LVTTL input for enabling outputs, active high. OE_0 for OUT0 / OUT0# OE_3 for OUT3 / OUT3# 3.3V LVTTL input for inverting the OE, SRC_STOP# and PWRDWN# pins. When 0 = same stage When 1 = OE_0, OE_3, SRC_STOP#, PWRDWN# inverted. 0.7V Differential outputs 3.3V LVTTL input for selecting fan-out of PLL operation. SMBus compatible SCLOCK input SMBus compatible SDATA External resistor connection to set the differential output current 3.3V LVTTL input for SRC stop, active low 3.3V LVTTL input for selecting the PLL bandwidth 3.3V LVTTL input for Power Down operation, active low 3.3V Power Supply for Outputs Ground for Outputs Ground for PLL 3.3V Power Supply for PLL
OE_INV
Input
25 6, 7, 9, 10, 19, 20, 22, 23 12 13 14 26 16 17 15 1, 5, 11, 18, 24 4 27 28
OUT[0:3] & OUT[0:3]# PLL/BYPASS# SCLK SDA IREF SRC_STOP# PLL_BW# PWRDWN# VDD VSS VSS_A VDD_A
Output Input Input I/O Input Input Input Input Power Ground Ground Power
Serial Data Interface (SMBus)
PI6C20400 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below.
Address assignment
A6 1 A5 1 A4 0 A3 1 A2 1 A1 1 A0 0 R/W 0/1
Data Protocol
1 bit Start bit 7 bits Slave Addr 1 R/W 1 Ack 8 bits Register offset 1 Ack 8 bits Byte Count =N 1 Ack 8 bits Data Byte 0 1 Ack ... 8 bits Data Byte N -1 1 Ack 1 bit Stop bit
Notes: 1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
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PI6C20400 1:4 Clock Driver for Intel PCI Express Chipsets Data Byte 0: Control Register
Bit 0 Descriptions Outputs Mode 0 = Divide by 2 1 = Normal PLL/BYPASS# 0 = Fanout 1 = PLL PLL Bandwidth 0 = High Bandwidth, 1 = Low Bandwidth TBD TBD TBD SRC_STOP# 0 = Driven when stopped 1 = Tristate PWRDWN# 0 = Driven when stopped 1 = Tristate RW 0 = Driven when stopped OUT[0:3], OUT[0:3]# Type RW Power Up Condition 1 = Normal Output(s) Affected OUT[0:3], OUT[0:3]# Source Pin NA
1
RW
1 = PLL
OUT[0:3], OUT[0:3]#
NA
2 3 4 5 6
RW
1 = Low
OUT[0:3], OUT[0:3]#
NA NA NA NA
7
RW
0 = Driven when stopped
OUT[0:3], OUT[0:3]#
NA
Data Byte 1: Control Register
Bit 0 1 2 3 4 5 6 7 OUTPUTS enable 1 = Enabled 0 = Disabled RW RW 1 = Enabled 1 = Enabled OUT2, OUT2# OUT3, OUT3# NA NA OUTPUTS enable 1 = Enabled 0 = Disabled RW RW 1 = Enabled 1 = Enabled OUT0, OUT0# OUT1, OUT1# NA NA Descriptions Type Power Up Condition Output(s) Affected Source Pin
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PI6C20400 1:4 Clock Driver for Intel PCI Express Chipsets Data Byte 2: Control Register
Bit 0 1 2 3 4 5 6 7 Allow control of OUTPUTS with assertion of SRC_STOP# 0 = Free running 1 = Stopped with SRC_Stop# RW RW 0 = Free running 0 = Free running OUT2, OUT2# OUT3, OUT3# NA NA Allow control of OUTPUTS with assertion of SRC_STOP# 0 = Free running 1 = Stopped with SRC_Stop# RW RW 0 = Free running 0 = Free running OUT0, OUT0# OUT1, OUT1# NA NA Descriptions Type Power Up Condition Output(s) Affected Source Pin
Data Byte 3: Control Register
Bit 0 1 2 3 4 5 6 7 TBD Descriptions Type RW RW RW RW RW RW RW RW Power Up Condition Output(s) Affected Source Pin
Data Byte 4: Pericom ID Register
Bit 0 1 2 3 4 5 6 7 Pericom ID Descriptions Type R R R R R R R R Power Up Condition 0 0 0 0 0 1 0 0 Output(s) Affected NA NA NA NA NA NA NA NA Pin NA NA NA NA NA NA NA NA
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PI6C20400 1:4 Clock Driver for Intel PCI Express Chipsets Functionality
PWRDWN# 1 0 OUT Normal IREF x 2 or Float OUT# Normal Low SRC_Stop# 1 0 OUT Normal IREF x 6 or Float OUT# Normal Low
Power Down (PWRDWN# assertion)
PWRDWN#
OUT OUT#
Figure 1. Power down sequence
Power Down (PWRDWN# De-assertion)
Tstable <1ms PWRDWN# OUT
OUT# Tdrive_PwrDwn# <300us, >200mV
Figure 2. Power down de-assert sequence
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PI6C20400 1:4 Clock Driver for Intel PCI Express Chipsets Current-mode output buffer characteristics of OUT[0:3], OUT[0:3]#
VDD (3.3V 5%)
Slope ~ 1/Rs RO IOUT ROS Iout VOUT = 0.85V max 0V 0.85V
Figure 9. Simplified diagram of current-mode output buffer
Differential Clock Buffer characteristics
Symbol RO ROS VOUT Minimum 3000 unspecified N/A Maximum N/A unspecified 850mV
Current Accuracy
Symbol IOUT Conditions VDD = 3.30 5% Configuration RREF = 475 1% IREF = 2.32mA Load Nominal test load for given configuration Min. -12% INOMINAL Max. +12% INOMINAL
Note: 1. INOMINAL refers to the expected current based on the configuration of the device.
Differential Clock Output Current
Board Target Trace/Term Z 100 (100 differential 15% coupling ratio) Reference R, Iref = VDD/(3xRr) RREF = 475 1%, IREF = 2.32mA Output Current IOH = 6 x IREF VOH @ Z 0.7V @ 50
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PI6C20400 1:4 Clock Driver for Intel PCI Express Chipsets Absolute Maximum Ratings (Over operating free-air temperature range)
Symbol VDD_A VDD VIH VIL Ts VESD 3.3V Core Supply Voltage 3.3V I/O Supply Voltage Input High Voltage Input Low Voltage Storage Temperature ESD Protection -0.5 -65 2000 150 C V Parameters Min. -0.5 -0.5 Max. 4.6 4.6 4.6 V Units
Note: 1. Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
DC Electrical Characteristics (VDD = 3.35%, VDD_A = 3.35%)
Symbol VDD_A VDD VIH VIL IIK VOH VOL IOH CIN COUT LPIN IDD ISS ISS TA Parameters 3.3V Core Supply Voltage 3.3V I/O Supply Voltage 3.3V Input High Voltage 3.3V Input Low Voltage Input Leakage Current 3.3V Output High Voltage 3.3V Output Low Voltage Output High Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Power Supply Current Power Down Current Power Down Current Ambient Temperature VDD = 3.465V, FCPU = 200MHz Driven outputs Tristate outputs 0 0 < VIN < VDD IOH = -1mA IOL = 1mA IOH = 6 x IREF, IREF = 2.32mA 12.2 15.6 3 5 6 7 200 40 12 70 C mA VDD Condition Min. 3.135 3.135 2.0 VSS - 0.3 -5 2.4 0.4 Max. 3.465 3.465 VDD + 0.3 0.8 +5 A V mA pF nH V Units
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PI6C20400 1:4 Clock Driver for Intel PCI Express Chipsets AC Switching Characteristics (VDD = 3.35%, VDD_A = 3.35%)
Symbol Trise / Tfall Trise / Tfall Rise and Fall Time Variation Rise/Fall Matching Tpd Tskew Tjitter VHIGH VLOW Vcross Vcross TDC PLL Mode Non-PLL Mode Output-to-Output Skew Cycle - Cycle Jitter Voltage High including overshoot Voltage Low including undershoot Absolute crossing point voltages Total Variation of Vcross over all edges Duty Cycle 45 660 -300 250 550 140 55 2.5 Parameters Rise and Fall Time (measured between 0.175V to 0.525V) Min 175 Max. 700 125 20 250 6.5 50 50 1150 Units ps ps % ps ns ps ps mV mV mV mV % 3 3 2 2 2 2 3 Notes 2 2 2
Notes: 1. Test configuration is Rs = 33.2, Rp = 49.9, and 2pF. 2. Measurement taken from Single Ended waveform. 3. Measurement taken from Differential waveform.
Configuration Test Load Board Termination
Rs 33 5% TLA PI6C20400 Rs 33 5% TLB 475 1% Rp 49.9 1% Rp 49.9 1% 2pF 5% 2pF 5% OUT# OUT
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PI6C20400 1:4 Clock Driver for Intel PCI Express Chipsets Packaging Mechanical: 28-Pin, 209-mil wide, 0.65mm pitch SSOP (H)
Packaging Mechanical: 28-Pin, 173-mil wide, 0.65mm pitch TSSOP (L)
28
.169 .177
4.3 4.5
1
.004 .008
.378 .386 9.6 9.8
0.09 0.20
0.45 0.75
.018 .030
.047 1.20 Max
.252 BSC 6.4
SEATING PLANE
.0256 BSC 0.65
.007 .012 0.19 0.30
.002 .006
0.05 0.15
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PI6C20400 1:4 Clock Driver for Intel PCI Express Chipsets Ordering Information
Ordering Code PI6C20400H PI6C20400HE PI6C20400L PI6C20400LE Package Code H HE L LE Package Description 28-pin, 209-mil wide, SSOP 28-pin, 209-mil wide, SSOP, Pb-Free and Green 28-pin, 173-mil wide, TSSOP 28-pin, 173-mil wide, TSSOP, Pb-Free and Green
Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
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